In many modern integrated circuits such as system-on-chips (SOCs), multiple clocks have become the norm. As a result, arbitration circuitry for handling clock domain crossings (CDCs) has become an integral part of many designs. Such arbitration circuitry may, for example, allow two processors operating in asynchronous clock domains to access a common single-ported memory. However, because the arbitration circuitry ultimately affects memory access latencies of both masters, its switching speed tends to be a critical design parameter.